Cmos High Efficiency Rf Power Amplifier

The design of an integrated CMOS Power Amplifier (PA) for a Jet Propulsion Laboratory (JPL) Synthetic Aperture Radar (SAR) mission is studied. Although there are a number of PA class definitions and published circuits, designing a high efficiency RF PA is still a challenging job. In this thesis, the goal is full integration in Silicon-on-Sapphire (SOS) using on-chip spiral inductors/transformers. A number of PAs are paralleled and the transformers, which have secondary sides in series, link the outputs in order to expand the output power up to 5W Peak Envelop Power (PEP). This thesis describes major classes of PAs and details class-D and class-E PAs. When the class-D PA is turned on more than half period, it improves virtual ground state in a differential amplifier structure providing immunity to bonding wire parasitic inductance problems. This modified class-D PA is named class-A/D. A class-E PA lacks bonding wire effects immunity. However, it has potential to decrease the number of transformers by using an output matching network. A representative, class-A/D 600 mW PA is designed and simulated in Agilent ADS. A differential structure gives a virtual ground to make the design immune to bonding wire parameters, and enables the PA to use center-tapped transformers. The transformers also link multiple output ports of PAs. The secondary spirals are connected in series such that low output voltage from each stage stacks up at the secondary. The simulated class-A/D PA has 660 mW output power, 51.6% drain efficiency and 45.3% Power Added Efficiency (PAE). A class-A/D 4-stage PA is also designed to output 5W PEP. This PA, compared to the previous 600 mW PA, does not degrade its performance seriously in simulation. The drain efficiency is 47.4 %, and PAE is 45.2 %. A layout floor plan of the class-A/D 4-stage PA is provided as a basis for further development. JPL and Kansas State University will refine the design and add a balun in the full integration. The other circuitry for a complete Transmitter/Receiver (T/R) module is being developed simultaneously. Ultimately, all the circuitry will be mounted on a one-chip T/R module.